A great number of modern communication systems, whether wired-based or wireless-based, are time-synchronized systems. In a time-synchronized communication system, one or more reference clocks are delivered from one or more clock sources to various devices in the system through a network. To increase the operation stabilities of the various devices in the communication system while also improving the flexibilities of these devices for different applications, there are generally more than one reference clock which are provided to these devices. However, in the event when the clock unit in a given device switches from one reference input clock to another reference input clock or when one or more of the reference input clocks fail, to ensure that the output of the clock unit maintains performance and clock stabilities, it is generally required that the clock unit include a “holdover” function and a holdover module to establish a stable output clock during such circumstances.
More specifically, in the communication systems, the holdover module is designed to perform the holdover function, i.e., to keep the output clock of the clock unit within a small error margin when the reference input clock is being switched, lost, or malfunctions, thereby ensuring the frequency stability of the output clock even when the reference input clock is being switched, lost, or malfunctions. The existing holdover modules are generally used in conjunction with a phase-locked loop (PLL). More specifically, a holdover module is typically configured to record the reference input clock or the state of the entire PLL when the reference input clock is stable. When the reference input clock is being switched, lost, or malfunctions, the holdover module is configured to apply the recorded reference input clock or the state of the entire PLL to an input of the PLL or to another point within the loop of the PLL to ensure that the output clock frequency remains stable.
However, existing implementations of the holdover function in a clock circuit/unit/module generally do not provide a satisfactory solution to both resolve the issue of frequency drift which might be caused by ambient temperature changes and at the same time maintain low jitter in the output clock. Hence, there is a need for a more effective holdover system and technique for these communication systems.